TSMC Readies Next-Gen HBM4 Base Dies, Built on 12nm and 5nm Nodes

Of the several major changes coming with HBM4 memory, one of the most immediate is the sheer width of the memory interface. With the fourth-generation memory standard moving from an already wide 1024-bit interface to a ultra-wide 2048-bit interface, HBM4 memory stacks won’t be business as usual; chip manufacturers are going to need to adopt more advanced packaging methods than are used today to accommodate the wider memory.

As part of its European Technology Symposium 2024 presentation, TSMC offered some fresh details into the base dies it will be manufacturing for HBM4, which will be built using logic processes. With TSMC planning to employ variations of their N12 and N5 processes for this task, the company is expecting to occupy a favorable place in the HBM4 manufacturing process, as memory fabs are not currently equipped to economically produce such advanced logic dies – if they can produce them at all.

For the first wave of HBM4, TSMC is preparing to use two fabrication processes: N12FFC+ and N5. While they serve the same purpose — integrating HBM4E memory with next-generation AI and HPC processors — they are going to be used in two different ways to connect memory for high-performance processors for AI and HPC applications.

“We are working with key HBM memory partners (Micron, Samsung, SK Hynix) over advanced nodes for HBM4 full stack integration,” said Senior Director of Design and Technology Platform at TSMC. “N12FFC+ cost effective base die can reach HBM for performance and N5 base die can provide even more logic with much lower power at HBM4 speeds.”

TSMC’s base die made on N12FFC+ fabrication process (12nm FinFet Compact Plus, which formally belongs to a 12nm-class technology, but it lays its roots from TSMC’s well-proven 16nm FinFET production node) will be used to install HBM4 memory stacks on a silicon interposer next to system-on-chips (SoCs). TSMC believes that their 12FFC+ process is well-suited to achieve HBM4 performance, enabling memory vendors to build 12-Hi(48 GB) and 16-Hi stacks (64 GB), with per-stack bandwidth well as over 2 TB/second. 

“We are also optimizing CoWoS-L and CoWoS-R for HBM4,” the Senior Director said. “Both CoWoS-L and CoWoS-R [use] over eight layers to enable HBM4’s routing of over 2,000 interconnects with [proper] signal integrity.”

HBM4 base dies on N12FFC+ will be instrumental in building system-in-packages (SiPs) using TSMC’s CoWoS-L or CoWoS-R advanced packaging technology, which offer interposers up to 8x reticle size – enough space for up to 12 HBM4 memory stacks. At present, HBM4 can achieve data transfer rates of 6 GT/s at currents of 14mA, according to TSMC figures.

“We collaborate with EDA partners like Cadence, Synopsys, and Ansys to certify HBM4 channel signal integrity, IR/EM, and thermal accuracy,” the TSMC representative explained.

Meanwhile, as an even more advanced alternative, memory manufacturers will also have the option of tapping TSMC’s N5 process for their HBM4 base dies. N5-built base dies will pack even more logic, consume less power, and will offer even higher performance. But arguably the most important benefit is that such an advanced process technology will enable are very small interconnect pitches, on the order of 6 to 9 microns. This will allow N5 base dies to be used in conjunction with direct bonding, enabling HBM4 to be 3D stacked right on top of logic chips. Direct bonding stands to allow for even greater memory performance, which is expected to be a big boost for AI and HPC chips that are always scrounging for more memory bandwidth.

We already know that TSMC and SK Hynix collaborate on HBM4 base dies. It is likely that TSMC will also produce HBM4 base dies for Micron. Otherwise, we’d be more surprised to see TSMC working with Samsung, as that conglomerate already has its own advanced logic fabs via its Samsung Foundry unit.

Source: Recent News