Enterprise

HP Expands DaaS Offerings: Apple Devices, HP VR Solutions, and Tech Café Market
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HP Expands DaaS Offerings: Apple Devices, HP VR Solutions, and Tech Café Market

Today, HP announced a new set of Device as a Service (DaaS) offerings for customers and channel partners. Notably, this includes the reveal of DaaS offerings for Apple devices, where HP will provide support for iPhone, iPad, Mac, and other Apple equipment. Along with expansion through Apple products, HP is also expanding their DaaS services to cover their own VR solutions. This includes the Z4 Workstation and the HP Windows Mixed Reality VR headset. HP aims to cover major customer pain points by unifying diverse fleets of different device types and OSes and free up IT resources.

HP DaaS program for Apple will cover dozens of SKU and include multiple versions of each device. Apple coverage includes accidental damage protection as well as next day onsite repair or replacement which can minimize downtime for the user increasing productivity. Part of this plan includes specialized endpoint management. These  HP experts are able to deploy applications, provision Wi-Fi access, and set and enforce security policies taking a load off internal IT resources. They are also able to find and protect data on devices that may have been lost or stolen. HP also offers optional services covering the entire device lifecycle from design and planning, as well as configuration and deployment services.  

HP is also expanding its real-time hardware analytics and proactive device management capabilities. The analytics are able to capture data including health monitoring (device to component level), security status reports as well analytics and reports for IT planning. Monitoring points such as CPU and Memory utilization, temperatures, battery and HDD life, Windows BSOD and software errors, and security policy compliance are some of the items which are monitored and analyzed. Some of the data can be used to proactively fix or update devices when a trend is recognized. HP says they have nearly 40 Million devices reporting non-PII (Personally Identifiable Information) into their analytics. HP is able to use this data to be able to spot trends and more quickly resolve issues with data collected from both the client level and the entire ‘data lake’ as HP called it. 

In addition to expanding the available devices and how they are managed, HP also introduced the Tech Cafe Market Enhanced. The Tech Café is an end-to-end smart vending and storage solution able to provide end-users immediate access to accessories and peripherals. A 24/7 locker for device swaps is available for quick exchange of devices for repair or new deployment. End users are able to easily access accessories or new devices directly from the lockers without a dedicated IT resource saving time and improving customer experience. HP can also manage ordering, stock replenishment, and reporting for the clients again with an aim to free up IT resources.

HP’s DaaS update continues to point the service in the direction of a complete end-to-end solution for commercial environments who would like to reduce expenses by essentially renting hardware, while still getting quality IT support for the ever-increasing amount of devices today’s workers have. Customers are able to get everything needed from hardware to lifecycle services intended to improve efficiency and free up IT resources. HP’s key value proposition is to deliver a lower total cost of ownership for getting the right product in the user’s hands. The rollout for DaaS programs for Apple is in North America now with plans to expand out to India and the Asia-Pacific region in the coming months. Both the new Z4 workstation and the HP Windows Mixed Reality headset is available now. 

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TYAN Announces AMD EPYC TN70A-B8026 Server: 1P, 16 DIMMs, 26 SSDs, OCuLink
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TYAN Announces AMD EPYC TN70A-B8026 Server: 1P, 16 DIMMs, 26 SSDs, OCuLink

TYAN introduced its first server and its first motherboard for AMD’s new EPYC processors. The company decided to take a cautious approach to AMD’s EPYC, and the initial machine will be a single-socket server for high-performance all-flash storage applications. Meanwhile, the new platforms from TYAN will be among the first applications to support OCuLink connections.

The first TYAN platform based on the AMD EPYC 7000-series processor capitalizes on the CPU’s primary advantage besides its core count (up to 32): the number of integrated PCIe 3.0 lanes (up to 128) that can be used to connect NVMe SSDs without any external switches or controllers. The TYAN TN70A-B8026 server is based on the S8026 motherboard that has 16 DDR4 DIMMs slots (two modules are supported per channel, 1 TB of DDR4 in total), two M.2-22110 slots for SSDs (PCIe 3.0 x4) as well as eight SFF-8611 PCIe/OCuLink x8 connectors for 24 hot-swap SSDs in U.2 form-factor. In total, the server supports 26 PCIe 3.0 x4 SSDs as well as two SATA devices.

The platform also supports five PCIe 3.0 x8 slots via 2U risers (these slots function when storage drives are not using their PCIe connections) as well as one PCIe 3.0 x16 OCP 2.0-capable slot for an EDR InfiniBand or a 100 GbE card. To support even the most power hungry components, TYAN equips its TN70A-B8026 with a redundant 770 W power supplies. As for management and networking, the machine is equipped with the AST2500 BMC with iKVM & Redfish support, two GbE ports (Broadcom BCM5720) for connectivity and one GbE for IPMI.

TYAN does not say which SSDs it’s going to use for the TN70A-B8026 and how many terabytes of storage in total the machine can support. What the company does say is that a pair of SFF-8611 OCuLink x8 connectors can be re-configured (from BIOS) to support up to 16 SATA 6 Gbps drives, which provides flexibility to server makers or value-add resellers, who plan to use the TYAN S8026 motherboard or the TN70A-B8026 server barebones. In fact, the latter fits into regular E-ATX supporting cases, so it can be used to build workstations with enhanced storage capabilities.

TYAN TN70A-B8026 Server Barebones SKUs
  PCIe Slots Storage Bays PSU UPC
B8026T70AV16E8HR 6 16 × 2.5″ SATA
8 × 2.5″ NVMe		 770 W redundant 635872043727
B8026T70AE24HR 2 24 × NVMe 635872043734

TYAN did not announce MSRP or ETA for its TN70A-B8026 server as well as the S8026 motherboard. Since the server can be equipped with different CPUs and SSDs, its price can vary by orders of magnitude and it does not make a lot of sense to make guesses at this point. Considering that high-endurance/high-capacity SSDs are quite expensive, a fully populated TYAN TN70A-B8026 machine can easily cross the $100K mark.

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AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2
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AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2

For users keeping track of AMD’s rollout of its new Zen microarchitecture, stage one was the launch of Ryzen, its new desktop-oriented product line last week. Stage three is the APU launch, focusing mainly on mobile parts. In the middle is stage two, Naples, and arguably the meatier element to AMD’s Zen story.

A lot of fuss has been made about Ryzen and Zen, with AMD’s re-launch back into high-performance x86. If you go by column inches, the consumer-focused Ryzen platform is the one most talked about and many would argue, the most important. In our interview with Dr. Lisa Su, CEO of AMD, the launch of Ryzen was a big hurdle in that journey. However, in the next sentence, Dr. Su lists Naples as another big hurdle, and if you decide to spend some time with one of the regular technology industry analysts, they will tell you that Naples is where AMD’s biggest chunk of the pie is. Enterprise is where the money is.

So while the consumer product line gets columns, the enterprise product line gets profits and high margins. Launching an enterprise product that gains even a few points of market share from the very large blue incumbent can implement billions of dollars to the bottom line, as well as provided some innovation as there are now two big players on the field. One could argue there are three players, if you consider ARM holds a few niche areas, however one of the big barriers to ARM adoption, aside from the lack of a high-performance single-core, is the transition from x86 to ARM instruction sets, requiring a rewrite of code. If AMD can rejoin and a big player in x86 enterprise, it puts a small stop on some of ARMs ambitions and aims to take a big enough chunk into Intel.

With today’s announcement, AMD is setting the scene for its upcoming Naples platform. Naples will not be the official name of the product line, and as we discussed with Dr. Su, Opteron one option being debated internally at AMD as the product name. Nonetheless, Naples builds on Ryzen, using the same core design but implementing it in a big way.

The top end Naples processor will have a total of 32 cores, with simultaneous multi-threading (SMT), to give a total of 64 threads. This will be paired with eight channels of DDR4 memory, up to two DIMMs per channel for a total of 16 DIMMs, and altogether a single CPU will support 128 PCIe 3.0 lanes. Naples also qualifies as a system-on-a-chip (SoC), with a measure of internal IO for storage, USB and other things, and thus may be offered without a chipset.

Naples will be offered as either a single processor platform (1P), or a dual processor platform (2P). In dual processor mode, and thus a system with 64 cores and 128 threads, each processor will use 64 of its PCIe lanes as a communication bus between the processors as part of AMD’s Infinity Fabric. The Infinity Fabric uses a custom protocol over these lanes, but bandwidth is designed to be on the order of PCIe. As each core uses 64 PCIe lanes to talk to the other, this allows each of the CPUs to give 64 lanes to the rest of the system, totaling 128 PCIe 3.0 again.

On the memory side, with eight channels and two DIMMs per channel, AMD is stating that they officially support up to 2TB of DRAM per socket, making 4TB in a single server. The total memory bandwidth available to a single CPU clocks in at 170 GB/s.

While not specifically mentioned in the announcement today, we do know that Naples is not a single monolithic die on the order of 500mm2 or up. Naples uses four of AMD’s Zeppelin dies (the Ryzen dies) in a single package. With each Zeppelin die coming in at 195.2mm2, if it were a monolithic die, that means a total of 780mm2 of silicon, and around 19.2 billion transistors – which is far bigger than anything Global Foundries has ever produced, let alone tried at 14nm. During our interview with Dr. Su, we postulated that multi-die packages would be the way forward on future process nodes given the difficulty of creating these large imposing dies, and the response from Dr. Su indicated that this was a prominent direction to go in.

Each die provides two memory channels, which brings us up to eight channels in total. However, each die only has 16 PCIe 3.0 lanes (24 if you want to count PCH/NVMe), meaning that some form of mux/demux, PCIe switch, or accelerated interface is being used. This could be extra silicon on package, given AMD’s approach of a single die variant of its Zen design to this point.

Note that we’ve seen multi-die packages before in previous products from both AMD and Intel. Despite both companies playing with multi-die or 2.5D technology (AMD with Fury, Intel with EMIB), we are lead to believe that these CPUs are similar to previous multi-chip designs, however there is Infinity Fabric going through them. At what bandwidth, we do not know at this point. It is also pertinent to note that there is a lot of talk going around about the strength of AMD’s Infinity Fabric, as well as how threads are manipulated within a silicon die itself, having two core complexes of four cores each. This is something we are investigating on the consumer side, but will likely be very relevant on the enterprise side as well.

In the land of benchmark numbers we can’t verify (yet), AMD showed demonstrations at the recent Ryzen Tech Day. The main demonstration was a sparse matrix calculation on a 3D-dataset for seismic analysis. In this test, solving a 15-diagonal matrix of 1 billion samples took 35 seconds on an Intel machine vs 18 seconds on an AMD machine (both machines using 44 cores and DDR4-1866). When allowed to use its full 64-cores and DDR4-2400 memory, AMD shaved another four seconds off. Again, we can’t verify these results, and it’s a single data point, but a diagonal matrix solver would be a suitable representation for an enterprise workload. We were told that the clock frequencies for each chip were at stock, however AMD did say that the Naples clocks were not yet finalized.

What we don’t know are power numbers, frequencies, processor lists, pricing, partners, segmentation, and all the meaty stuff. We expect AMD to offer a strong attack on the 1P/2P server markets, which is where 99% of the enterprise is focused, particularly where high-performance virtualization is needed, or storage. How Naples migrates into the workstation space is an unknown, but I hope it does. We’re working with AMD to secure samples for Johan and me in advance of the Q2 launch.

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AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2
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AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2

For users keeping track of AMD’s rollout of its new Zen microarchitecture, stage one was the launch of Ryzen, its new desktop-oriented product line last week. Stage three is the APU launch, focusing mainly on mobile parts. In the middle is stage two, Naples, and arguably the meatier element to AMD’s Zen story.

A lot of fuss has been made about Ryzen and Zen, with AMD’s re-launch back into high-performance x86. If you go by column inches, the consumer-focused Ryzen platform is the one most talked about and many would argue, the most important. In our interview with Dr. Lisa Su, CEO of AMD, the launch of Ryzen was a big hurdle in that journey. However, in the next sentence, Dr. Su lists Naples as another big hurdle, and if you decide to spend some time with one of the regular technology industry analysts, they will tell you that Naples is where AMD’s biggest chunk of the pie is. Enterprise is where the money is.

So while the consumer product line gets columns, the enterprise product line gets profits and high margins. Launching an enterprise product that gains even a few points of market share from the very large blue incumbent can implement billions of dollars to the bottom line, as well as provided some innovation as there are now two big players on the field. One could argue there are three players, if you consider ARM holds a few niche areas, however one of the big barriers to ARM adoption, aside from the lack of a high-performance single-core, is the transition from x86 to ARM instruction sets, requiring a rewrite of code. If AMD can rejoin and a big player in x86 enterprise, it puts a small stop on some of ARMs ambitions and aims to take a big enough chunk into Intel.

With today’s announcement, AMD is setting the scene for its upcoming Naples platform. Naples will not be the official name of the product line, and as we discussed with Dr. Su, Opteron one option being debated internally at AMD as the product name. Nonetheless, Naples builds on Ryzen, using the same core design but implementing it in a big way.

The top end Naples processor will have a total of 32 cores, with simultaneous multi-threading (SMT), to give a total of 64 threads. This will be paired with eight channels of DDR4 memory, up to two DIMMs per channel for a total of 16 DIMMs, and altogether a single CPU will support 128 PCIe 3.0 lanes. Naples also qualifies as a system-on-a-chip (SoC), with a measure of internal IO for storage, USB and other things, and thus may be offered without a chipset.

Naples will be offered as either a single processor platform (1P), or a dual processor platform (2P). In dual processor mode, and thus a system with 64 cores and 128 threads, each processor will use 64 of its PCIe lanes as a communication bus between the processors as part of AMD’s Infinity Fabric. The Infinity Fabric uses a custom protocol over these lanes, but bandwidth is designed to be on the order of PCIe. As each core uses 64 PCIe lanes to talk to the other, this allows each of the CPUs to give 64 lanes to the rest of the system, totaling 128 PCIe 3.0 again.

On the memory side, with eight channels and two DIMMs per channel, AMD is stating that they officially support up to 2TB of DRAM per socket, making 4TB in a single server. The total memory bandwidth available to a single CPU clocks in at 170 GB/s.

While not specifically mentioned in the announcement today, we do know that Naples is not a single monolithic die on the order of 500mm2 or up. Naples uses four of AMD’s Zeppelin dies (the Ryzen dies) in a single package. With each Zeppelin die coming in at 195.2mm2, if it were a monolithic die, that means a total of 780mm2 of silicon, and around 19.2 billion transistors – which is far bigger than anything Global Foundries has ever produced, let alone tried at 14nm. During our interview with Dr. Su, we postulated that multi-die packages would be the way forward on future process nodes given the difficulty of creating these large imposing dies, and the response from Dr. Su indicated that this was a prominent direction to go in.

Each die provides two memory channels, which brings us up to eight channels in total. However, each die only has 16 PCIe 3.0 lanes (24 if you want to count PCH/NVMe), meaning that some form of mux/demux, PCIe switch, or accelerated interface is being used. This could be extra silicon on package, given AMD’s approach of a single die variant of its Zen design to this point.

Note that we’ve seen multi-die packages before in previous products from both AMD and Intel. Despite both companies playing with multi-die or 2.5D technology (AMD with Fury, Intel with EMIB), we are lead to believe that these CPUs are similar to previous multi-chip designs, however there is Infinity Fabric going through them. At what bandwidth, we do not know at this point. It is also pertinent to note that there is a lot of talk going around about the strength of AMD’s Infinity Fabric, as well as how threads are manipulated within a silicon die itself, having two core complexes of four cores each. This is something we are investigating on the consumer side, but will likely be very relevant on the enterprise side as well.

In the land of benchmark numbers we can’t verify (yet), AMD showed demonstrations at the recent Ryzen Tech Day. The main demonstration was a sparse matrix calculation on a 3D-dataset for seismic analysis. In this test, solving a 15-diagonal matrix of 1 billion samples took 35 seconds on an Intel machine vs 18 seconds on an AMD machine (both machines using 44 cores and DDR4-1866). When allowed to use its full 64-cores and DDR4-2400 memory, AMD shaved another four seconds off. Again, we can’t verify these results, and it’s a single data point, but a diagonal matrix solver would be a suitable representation for an enterprise workload. We were told that the clock frequencies for each chip were at stock, however AMD did say that the Naples clocks were not yet finalized.

What we don’t know are power numbers, frequencies, processor lists, pricing, partners, segmentation, and all the meaty stuff. We expect AMD to offer a strong attack on the 1P/2P server markets, which is where 99% of the enterprise is focused, particularly where high-performance virtualization is needed, or storage. How Naples migrates into the workstation space is an unknown, but I hope it does. We’re working with AMD to secure samples for Johan and me in advance of the Q2 launch.

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