CPUs


AMD Launches Excavator on Desktop: The 65W Athlon X4 845 for $70

AMD Launches Excavator on Desktop: The 65W Athlon X4 845 for $70

As part of today’s launch AMD released two new Kaveri based APUs as part of the FM2+ platform, the A10-7860K and the A6-7470K, as well as clarifying the way the new 125W Wraith stock cooler would be distributed at this time. What went under the radar almost was the release of a third part, the Athlon X4 845 CPU, featuring no integrated graphics but AMD’s newest architecture instead.

This makes good timing, because our review of AMD’s Carrizo, the mobile platform using the latest AMD architecture is set to go up in the next couple of days. AMD’s Excavator cores were the poignant part of AMD’s Tech Day in mid-2015, where the new Excavator architecture was discussed and especially in relation to the previous generation Steamroller cores.

The goal of Excavator, as we were told at the time, was to develop a series of big steps into improving the efficiency of the base Bulldozer microarchitecture through high density libraries, better metal stacks in production, more on-chip analysis to save power, more power planes to regulate those chances and everything in-between. We were told we wouldn’t see the Excavator core on the desktop in its desktop form because the design focused on the 15W-35W power window, rather than the 45W+ on the desktop.

Fast forward to today and there seems to be a slight reversal here. The new AMD Athlon X4 845 is a pair of Excavator modules in a desktop package, designed to slot right in where the Steamroller design through Kaveri has been sitting for a couple of years. Why the change? And why a single SKU at 65W, way off the 15W-35W range quoted as ‘ideal’ back at the Tech Day?

AMD Excavator Based Lineup
  A12 PRO-
8800B
FX-
8800P
A10-
8700P
A8-
8600P
A6-PRO
8500B
Athlon X4
845
Platform Mobile Mobile Mobile Mobile Mobile Desktop
Modules 2 2 2 2 1 2
Threads 4 4 4 4 2 4
Core Freq. (GHz) 2.1-3.4 2.1-3.4 1.8-3.2 1.6-3.0 1.6-3.0 3.5-3.8
Compute Units 4+8 4+8 4+6 4+6 2+4 4+0
Streaming
Processors
512 512 384 384 256 N/A
IGP Freq. (MHz) 800 800 800 720 800 N/A
TDP 15-35W 15-35W 15W 15W 15W 65W
DRAM
Frequency
2133 2133 2133 2133 1600 2133
L2 Cache 2x1MB 2x1MB 2x1MB 2x2MB 2x1MB 2x1MB

One thing that was made perfectly clear in AMD’s briefing on the new Athlon was that this is not a performance part – due to the nature of Excavator the new CPU would be purely an efficiency play, allowing customers to take advantage of the latest architecture in the desktop if they didn’t need the full-fat performance. Arguably you could already find Excavator in the desktop, through Dell’s Inspiron 3656 range which uses a mobile part in a desktop case with a discrete graphics card.

With the new Athlon, the fact that there is no graphics part to the FM2+ processor does raise several questions. Is this a new die specifically for the Excavator on desktop, which might run into the tens of millions of dollars to produce, or is it repurposed mobile silicon put into a desktop package. Instinct tells us it’s the latter, perhaps better binned parts to show that the core can do 3.8 GHz at 65W, but at the expense of the integrated graphics, or due to production issues the integrated graphics on die are unusable.  One of the interesting things is also the L2 cache situation, because the Excavator modules in Carrizo were designed with 1MB of L2 per module, rather than the 2MB of L2 cache per module in desktop Kaveri. This is somewhat balanced by the larger L1 data cache in Excavator, but because there is no L3 cache either, it has to rely on other Excavator enhancements (better prefetch, wider prefetch windows) in order to bring it up to speed.

The PCIe 3.0 lanes are also at x8, which is another mobile limitation rather than the result of the PCIe root complex being half-disabled.

AMD has already stated that the next generation of AMD APUs will be on the AM4 platform, code named Bristol Ridge and Summit Ridge. We assume Bristol Ridge to be Excavator based, because there has to be something between now and Zen, but it would seem to suggest that the Excavator memory controller has support for DDR3 and DDR4, similar to what was suggested when AMD announced their DDR4-capable R-series APUs for embedded late last year. This may mean that AM4 supports both DDR3 and DDR4 as a result, which would not be unsurprising given how most DRAM transitions go.

We have asked for samples when they start to circulate. The Athlon X4 845 will have a MSRP of $70.

Source: AMD

Additional, 3rd Feb: We have been told by AMD that ‘The Athlon X4 845 is based on the “Carrizo” die with the GPU and FCH disabled. [T]he Athlon X4 845 supports DDR3 memory at speeds up to 2133MHz.’. Also, despite the focus on efficiency, the X4 845 will not have a configurable TDP.

AMD Launches Excavator on Desktop: The 65W Athlon X4 845 for $70

AMD Launches Excavator on Desktop: The 65W Athlon X4 845 for $70

As part of today’s launch AMD released two new Kaveri based APUs as part of the FM2+ platform, the A10-7860K and the A6-7470K, as well as clarifying the way the new 125W Wraith stock cooler would be distributed at this time. What went under the radar almost was the release of a third part, the Athlon X4 845 CPU, featuring no integrated graphics but AMD’s newest architecture instead.

This makes good timing, because our review of AMD’s Carrizo, the mobile platform using the latest AMD architecture is set to go up in the next couple of days. AMD’s Excavator cores were the poignant part of AMD’s Tech Day in mid-2015, where the new Excavator architecture was discussed and especially in relation to the previous generation Steamroller cores.

The goal of Excavator, as we were told at the time, was to develop a series of big steps into improving the efficiency of the base Bulldozer microarchitecture through high density libraries, better metal stacks in production, more on-chip analysis to save power, more power planes to regulate those chances and everything in-between. We were told we wouldn’t see the Excavator core on the desktop in its desktop form because the design focused on the 15W-35W power window, rather than the 45W+ on the desktop.

Fast forward to today and there seems to be a slight reversal here. The new AMD Athlon X4 845 is a pair of Excavator modules in a desktop package, designed to slot right in where the Steamroller design through Kaveri has been sitting for a couple of years. Why the change? And why a single SKU at 65W, way off the 15W-35W range quoted as ‘ideal’ back at the Tech Day?

AMD Excavator Based Lineup
  A12 PRO-
8800B
FX-
8800P
A10-
8700P
A8-
8600P
A6-PRO
8500B
Athlon X4
845
Platform Mobile Mobile Mobile Mobile Mobile Desktop
Modules 2 2 2 2 1 2
Threads 4 4 4 4 2 4
Core Freq. (GHz) 2.1-3.4 2.1-3.4 1.8-3.2 1.6-3.0 1.6-3.0 3.5-3.8
Compute Units 4+8 4+8 4+6 4+6 2+4 4+0
Streaming
Processors
512 512 384 384 256 N/A
IGP Freq. (MHz) 800 800 800 720 800 N/A
TDP 15-35W 15-35W 15W 15W 15W 65W
DRAM
Frequency
2133 2133 2133 2133 1600 2133
L2 Cache 2x1MB 2x1MB 2x1MB 2x2MB 2x1MB 2x1MB

One thing that was made perfectly clear in AMD’s briefing on the new Athlon was that this is not a performance part – due to the nature of Excavator the new CPU would be purely an efficiency play, allowing customers to take advantage of the latest architecture in the desktop if they didn’t need the full-fat performance. Arguably you could already find Excavator in the desktop, through Dell’s Inspiron 3656 range which uses a mobile part in a desktop case with a discrete graphics card.

With the new Athlon, the fact that there is no graphics part to the FM2+ processor does raise several questions. Is this a new die specifically for the Excavator on desktop, which might run into the tens of millions of dollars to produce, or is it repurposed mobile silicon put into a desktop package. Instinct tells us it’s the latter, perhaps better binned parts to show that the core can do 3.8 GHz at 65W, but at the expense of the integrated graphics, or due to production issues the integrated graphics on die are unusable.  One of the interesting things is also the L2 cache situation, because the Excavator modules in Carrizo were designed with 1MB of L2 per module, rather than the 2MB of L2 cache per module in desktop Kaveri. This is somewhat balanced by the larger L1 data cache in Excavator, but because there is no L3 cache either, it has to rely on other Excavator enhancements (better prefetch, wider prefetch windows) in order to bring it up to speed.

The PCIe 3.0 lanes are also at x8, which is another mobile limitation rather than the result of the PCIe root complex being half-disabled.

AMD has already stated that the next generation of AMD APUs will be on the AM4 platform, code named Bristol Ridge and Summit Ridge. We assume Bristol Ridge to be Excavator based, because there has to be something between now and Zen, but it would seem to suggest that the Excavator memory controller has support for DDR3 and DDR4, similar to what was suggested when AMD announced their DDR4-capable R-series APUs for embedded late last year. This may mean that AM4 supports both DDR3 and DDR4 as a result, which would not be unsurprising given how most DRAM transitions go.

We have asked for samples when they start to circulate. The Athlon X4 845 will have a MSRP of $70.

Source: AMD

Additional, 3rd Feb: We have been told by AMD that ‘The Athlon X4 845 is based on the “Carrizo” die with the GPU and FCH disabled. [T]he Athlon X4 845 supports DDR3 memory at speeds up to 2133MHz.’. Also, despite the focus on efficiency, the X4 845 will not have a configurable TDP.

Skylake Iris Pro hits Intel’s Pricing Lists: Xeon E3-1575M v5 with GT4e

Skylake Iris Pro hits Intel’s Pricing Lists: Xeon E3-1575M v5 with GT4e

One of our forum members, Sweepr, posted Intel’s latest pricing list for OEMs dated the 24th of January and it contained a number of interesting parts worth documenting.  The Braswell parts and Skylake Celerons were disclosed over the past few months are now available to OEMs, but it’s the parts with Iris Pro that have our attention.

Iris Pro is Intel’s name for their high end graphics solution. Using their latest graphics microarchitecture, Gen9, Iris Pro packs in the most execution units (72) as well as a big scoop of eDRAM. At the minute we assume it’s the 128 MB edition as Intel’s roadmaps have stated a 4+4e part only on mobile, rather than a 4+3e part with 64 MB (only the 2+3e parts are listed as 64MB), although we are looking for confirmation.

The new parts are listed as:

Xeon E3-1575M v5 (8M cache, 4 Cores, 8 Threads, 3.00 GHz, 14nm) – $1,207
Xeon E3-1545M v5 (8M cache, 4 Cores, 8 Threads, 2.90 GHz, 14nm) – $679
Xeon E3-1515M v5 (8M cache, 4 Cores, 8 Threads, 2.80 GHz, 14nm) – $489

These will compare to the non-Iris Pro counterparts, running P530 graphics (4+2, 24 EUs):

Xeon E3-1535M v5 (8M cache, 4 Cores, 8 Threads, 2.90 GHz, 14nm) – $623
Xeon E3-1505M v5 (8M cache, 4 Cores, 8 Threads, 2.80 GHz, 14nm) – $434

As Sweepr points out, the difference between the 2.8-2.9 GHz parts is only $55-56. That is for both the increase in graphics EUs (24 to 72) as well as that extra on-package eDRAM.


The i7-4950HQ with 128 MB eDRAM

We have more reasons to be excited over the eDRAM in Skylake than what we saw before in Haswell with the i7-4950HQ on mobile and Broadwell on desktop with the i7-5775C, i5-5765C and the relevant Xeons. With the older platforms, the eDRAM was not a proper bidirectional cache per se.  It was used as a victim cache, such that data that was spurned from the L3 cache on the CPU ended up in eDRAM, but the CPU could not place data from the DRAM into the eDRAM without using it first (prefetch prediction). This also meant that the eDRAM was invisible to any other devices on the system, and without specific hooks couldn’t be used by most software or peripherals.

With Skylake, this changes, the eDRAM lies beyond the L3 and the System Agent as a pathway to DRAM, meaning that any data that wants DRAM space will go through the eDRAM in search for it. Rather than acting as a pseudo-L4 cache, the eDRAM becomes a DRAM buffer and automatically transparent to any software (CPU or IGP) that requires DRAM access. As a result, other hardware that communicates through the system agent (such as PCIe devices or data from the chipset) and requires information in DRAM does not need to navigate through the L3 cache on the processor.  Technically graphics workloads still need to circle around the system agent, perhaps drawing a little more power, but GPU drivers need not worry about the size of the eDRAM when it becomes buffer-esque and is accessed before the memory controller is adjusted into a higher power read request. The underlying message is that the eDRAM is now observed by all DRAM accesses, allowing it to be fully coherent and no need for it to be flushed to maintain that coherence. Also, for display engine tasks, it can bypass the L3 when required in a standard DRAM access scenario. While the purpose of the eDRAM is to be as seamless as possible, Intel is allowing some level on control at the driver level allowing textures larger than the L3 to reside only in eDRAM in order to prevent overwriting the data contained in the L3 and having to recache it for other workloads.

We go into more detail on the changes to Skylake’s eDRAM in our microarchitecture analysis piece, back from September.

The fact that Intel is approaching the mobile Xeon market first, rather than the consumer market as in Haswell, should be noted. eDRAM has always been seen as a power play for heavy DRAM workloads, which arguably occur more in professional environments. That still doesn’t stop desktop users requesting it as well – the fact that the jump from 4+2 to a 4+4e package is only $55-$56 means that if we apply the same metrics to desktop processors, an i5-6600K with eDRAM would be $299 in retail (vs. $243 MSRP on the standard i5-6600K).

One of the big tasks this year will be to see how the eDRAM, in the new guise as a DRAM buffer, makes a difference to consumer and enterprise workloads. Now that there are two pairs of CPUs on Intel’s pricing list that are identical aside from the eDRAM, we have to go searching for a source. It seems that HP has already released a datasheet showing the HP ZBook 17 G3 Mobile Workstation as being offered with the E3-1575 v5, which Intel lists as a whopping $1207. That’s certainly not the extra $55.

Source: AnandTech Forums, Intel

Skylake Iris Pro hits Intel’s Pricing Lists: Xeon E3-1575M v5 with GT4e

Skylake Iris Pro hits Intel’s Pricing Lists: Xeon E3-1575M v5 with GT4e

One of our forum members, Sweepr, posted Intel’s latest pricing list for OEMs dated the 24th of January and it contained a number of interesting parts worth documenting.  The Braswell parts and Skylake Celerons were disclosed over the past few months are now available to OEMs, but it’s the parts with Iris Pro that have our attention.

Iris Pro is Intel’s name for their high end graphics solution. Using their latest graphics microarchitecture, Gen9, Iris Pro packs in the most execution units (72) as well as a big scoop of eDRAM. At the minute we assume it’s the 128 MB edition as Intel’s roadmaps have stated a 4+4e part only on mobile, rather than a 4+3e part with 64 MB (only the 2+3e parts are listed as 64MB), although we are looking for confirmation.

The new parts are listed as:

Xeon E3-1575M v5 (8M cache, 4 Cores, 8 Threads, 3.00 GHz, 14nm) – $1,207
Xeon E3-1545M v5 (8M cache, 4 Cores, 8 Threads, 2.90 GHz, 14nm) – $679
Xeon E3-1515M v5 (8M cache, 4 Cores, 8 Threads, 2.80 GHz, 14nm) – $489

These will compare to the non-Iris Pro counterparts, running P530 graphics (4+2, 24 EUs):

Xeon E3-1535M v5 (8M cache, 4 Cores, 8 Threads, 2.90 GHz, 14nm) – $623
Xeon E3-1505M v5 (8M cache, 4 Cores, 8 Threads, 2.80 GHz, 14nm) – $434

As Sweepr points out, the difference between the 2.8-2.9 GHz parts is only $55-56. That is for both the increase in graphics EUs (24 to 72) as well as that extra on-package eDRAM.


The i7-4950HQ with 128 MB eDRAM

We have more reasons to be excited over the eDRAM in Skylake than what we saw before in Haswell with the i7-4950HQ on mobile and Broadwell on desktop with the i7-5775C, i5-5765C and the relevant Xeons. With the older platforms, the eDRAM was not a proper bidirectional cache per se.  It was used as a victim cache, such that data that was spurned from the L3 cache on the CPU ended up in eDRAM, but the CPU could not place data from the DRAM into the eDRAM without using it first (prefetch prediction). This also meant that the eDRAM was invisible to any other devices on the system, and without specific hooks couldn’t be used by most software or peripherals.

With Skylake, this changes, the eDRAM lies beyond the L3 and the System Agent as a pathway to DRAM, meaning that any data that wants DRAM space will go through the eDRAM in search for it. Rather than acting as a pseudo-L4 cache, the eDRAM becomes a DRAM buffer and automatically transparent to any software (CPU or IGP) that requires DRAM access. As a result, other hardware that communicates through the system agent (such as PCIe devices or data from the chipset) and requires information in DRAM does not need to navigate through the L3 cache on the processor.  Technically graphics workloads still need to circle around the system agent, perhaps drawing a little more power, but GPU drivers need not worry about the size of the eDRAM when it becomes buffer-esque and is accessed before the memory controller is adjusted into a higher power read request. The underlying message is that the eDRAM is now observed by all DRAM accesses, allowing it to be fully coherent and no need for it to be flushed to maintain that coherence. Also, for display engine tasks, it can bypass the L3 when required in a standard DRAM access scenario. While the purpose of the eDRAM is to be as seamless as possible, Intel is allowing some level on control at the driver level allowing textures larger than the L3 to reside only in eDRAM in order to prevent overwriting the data contained in the L3 and having to recache it for other workloads.

We go into more detail on the changes to Skylake’s eDRAM in our microarchitecture analysis piece, back from September.

The fact that Intel is approaching the mobile Xeon market first, rather than the consumer market as in Haswell, should be noted. eDRAM has always been seen as a power play for heavy DRAM workloads, which arguably occur more in professional environments. That still doesn’t stop desktop users requesting it as well – the fact that the jump from 4+2 to a 4+4e package is only $55-$56 means that if we apply the same metrics to desktop processors, an i5-6600K with eDRAM would be $299 in retail (vs. $243 MSRP on the standard i5-6600K).

One of the big tasks this year will be to see how the eDRAM, in the new guise as a DRAM buffer, makes a difference to consumer and enterprise workloads. Now that there are two pairs of CPUs on Intel’s pricing list that are identical aside from the eDRAM, we have to go searching for a source. It seems that HP has already released a datasheet showing the HP ZBook 17 G3 Mobile Workstation as being offered with the E3-1575 v5, which Intel lists as a whopping $1207. That’s certainly not the extra $55.

Source: AnandTech Forums, Intel

Intel Launches Skylake vPro With Intel Authenticate

Intel Launches Skylake vPro With Intel Authenticate

Intel’s vPro technology has been around for quite a while now, and with every new processor generation they seem to always add more features under the vPro umbrella. For a comprehensive look at what is existing now, check out the vPro launch for…