In the eternal battle to drive more details out of AMD ahead of the full launch of its new Zen microarchitecture based CPUs, today AMD is lifting the lid on some new features in order to whet the appetite (and appease the hype-train, perhaps) and that…
As part of the European Digital Infrastructure Summit in London this week, Microsoft’s Azure team will be lifting the lid on Project Olympus, the next generation hyperscale cloud hardware design and model for open source hardware development, in collaboration with the Open Compute Project (OCP). Project Olympus is being described as a way to embrace future platforms in a standardized design, much like other OCP projects, and the open source standards behind the platform are offering insights into Intel’s Skylake-EP Platform, known as Purley.
It seems odd for information about Skylake-EP to be sanctioned at this time (technically none of the documents mention Intel, Skylake or Purley, but it can be deciphered as below), especially given the recent release of Broadwell-E/EP and Intel’s previous stance of limited data release prior to launch. It would appear that the information Microsoft are providing at the summit has been sanctioned, however sometimes putting two plus two together requires a little digging.
All this information is posted on the Microsoft Azure blog, which links directly to the OCP pages where motherboard specifications and server mechanical specifications are provided in PDF format.
Being the motherboard guy at AnandTech, I skipped straight to the motherboard information. Page 31 of the motherboard document gives the following example motherboard drawing:
Here is a dual-socket design, with a set of PCIe slots, some power connectors and other I/O components (some fiber Ethernet, for example). But jam packed in the middle are two very large sockets. We’ve seen these before, back at Supercomputing 2015 when Intel announced Knights Landing, which is a Xeon Phi product:
Xeon Phi’s Knights Landing design uses an LGA3647 implementation based on its 72 cores, 16GB of MCDRAM, and six memory channels. There are a lot of pins because there’s a lot to power up.
In previous generations of EP processors, both EP and E have shared the same socket. If I wanted to use my E5-2699 v4 Broadwell-EP LGA2011-3 processor in an X99 consumer motherboard instead of an i7-6950X, I could. Essentially all the Core and all the Xeon E5 CPUs have shared a common socket, making it easy for 1P/2P/4P processors to share around. If Purley / Skylake-EP uses the LGA3647 socket, this means one of four things.
The first is that this might not be Skylake-EP, and something odd like Skylake-EN.
The second is that Skylake-E will also share the same socket, and be LGA3647. This sounds somewhat implausible, given that Skylake-EP will have to handle at least the same amount of cores as Broadwell-EP, so there would be a lot of pins on a consumer platform for no reason.
The third possibility is that Skylake-E and Skylake-EP are going to be different sockets. This would indicate a split between consumer HEDT and dual-socket workstations and servers. Given previous generational changes, Skylake-E for consumers is expected to follow a similar pattern – around 2000 pins in a single socket design. However if Skylake-EP is making the jump to a significantly larger socket, especially for 2P workstation and server designs, it will produce a spread of difference in potential for pricing structures and implementation.
The fourth possibility extends from the third, and that Skylake-EP will have two socket designs depending on the size of the core. For Broadwell-EP, there were three designs for the silicon underneath – a low core count (LCC), a medium core count (MCC) and an extreme core count (XCC). If Intel are splitting up the sockets, it may be the case that only the XCC or MCC+XCC sides of the equation are using LGA3647. LCC designs are typically used for the consumer E series parts anyway, so Intel may decide to make the low core designs of EP on the smaller socket. There’s a wealth of possibility here.
On the main Microsoft Azure page, a handy diagram of an example machine was provided (with some areas blacked out):
Here we see that motherboard from the image above, using two low profile heatsinks with copper piping feeding an optional heatsink inside the chassis. To the sides of each of the sockets are big black squares, indicating where the DDR4 memory should go. Nearer the bottom of the board are networking implementations (50G is labeled), and PCIe slots suitable for three full-height, half-length (FHHL) PCIe cards. Interestingly on the right-hand side, we have labeled ‘up to 8 M.2 NVMe SSDs’.
Back to the motherboard specification, we see the list of blacked out areas along with a more comprehensive sequence of potential configurations:
There are spots for up to 32 DIMMs, which makes 16 per socket. Depending on how many memory controllers the CPU has, this could mean 8-channel and 2 DIMMs per channel (DPC), or 4-channel and 4 DPC. Nowhere does it state the maximum DRAM support per CPU, but DDR4 LRDIMMs are currently at 256GB/module, meaning a potential maximum of 4TB per CPU or 8TB per system. We expect Skylake-EP to support 3D XPoint at some stage as well.
On that list of support also mentions up to 12 SATA devices, up to 3 FHHL cards, and two PCIe x8 slots capable of supporting two M.2 modules each. So this is where that 8x M.2 comes in – if we get four from two PCIe x8 slots, and combine this with up to four M.2 direct attach modules, that makes eight.
The top-level block diagram is also worth a look. Patrick from STH specifically points out the PCIe 3.0 support for the platform:
On the right-hand side, adding up all the PCIe numbers and it comes to 88 PCIe 3.0 lanes, or 44 per CPU. This would be an upgrade on the 40 lanes per CPU currently on Broadwell-EP. There is also provision for PCIe lanes to be used with the mini-SAS connectors on the left-hand side. Technically the BMC also requires a PCIe link as well.
Given the long product cycles of Intel’s EP platforms, and the fact that the Big Seven cloud providers have a lot of clout over sales means they are most likely testing and integrating the next generation hardware. The release to the public, and smaller players in the OCP space, is a long and slow one. We’re not expecting Skylake-E/EP out until well into 2017, if not the year after, so information will certainly be on the slow burn. Supercomputing 2016 is happening in Utah in a couple of weeks, and although we won’t be there due to scheduling, something may pop out of the woodwork. We’ll keep our eyes peeled.
Source: Microsoft, ServeTheHome
SuperComputing 15: Intel’s Knights Landing / Xeon Phi Silicon on Display
A Few Notes on Intel’s Knights Landing and MCDRAM Modes from SC15
The Next Generation Open Compute Hardware: Tried and Tested
The Intel Xeon E5 v4 Review: Testing Broadwell-EP With Demanding Server Workloads
As part of the European Digital Infrastructure Summit in London this week, Microsoft’s Azure team will be lifting the lid on Project Olympus, the next generation hyperscale cloud hardware design and model for open source hardware development, in collaboration with the Open Compute Project (OCP). Project Olympus is being described as a way to embrace future platforms in a standardized design, much like other OCP projects, and the open source standards behind the platform are offering insights into Intel’s Skylake-EP Platform, known as Purley.
It seems odd for information about Skylake-EP to be sanctioned at this time (technically none of the documents mention Intel, Skylake or Purley, but it can be deciphered as below), especially given the recent release of Broadwell-E/EP and Intel’s previous stance of limited data release prior to launch. It would appear that the information Microsoft are providing at the summit has been sanctioned, however sometimes putting two plus two together requires a little digging.
All this information is posted on the Microsoft Azure blog, which links directly to the OCP pages where motherboard specifications and server mechanical specifications are provided in PDF format.
Being the motherboard guy at AnandTech, I skipped straight to the motherboard information. Page 31 of the motherboard document gives the following example motherboard drawing:
Here is a dual-socket design, with a set of PCIe slots, some power connectors and other I/O components (some fiber Ethernet, for example). But jam packed in the middle are two very large sockets. We’ve seen these before, back at Supercomputing 2015 when Intel announced Knights Landing, which is a Xeon Phi product:
Xeon Phi’s Knights Landing design uses an LGA3647 implementation based on its 72 cores, 16GB of MCDRAM, and six memory channels. There are a lot of pins because there’s a lot to power up.
In previous generations of EP processors, both EP and E have shared the same socket. If I wanted to use my E5-2699 v4 Broadwell-EP LGA2011-3 processor in an X99 consumer motherboard instead of an i7-6950X, I could. Essentially all the Core and all the Xeon E5 CPUs have shared a common socket, making it easy for 1P/2P/4P processors to share around. If Purley / Skylake-EP uses the LGA3647 socket, this means one of four things.
The first is that this might not be Skylake-EP, and something odd like Skylake-EN.
The second is that Skylake-E will also share the same socket, and be LGA3647. This sounds somewhat implausible, given that Skylake-EP will have to handle at least the same amount of cores as Broadwell-EP, so there would be a lot of pins on a consumer platform for no reason.
The third possibility is that Skylake-E and Skylake-EP are going to be different sockets. This would indicate a split between consumer HEDT and dual-socket workstations and servers. Given previous generational changes, Skylake-E for consumers is expected to follow a similar pattern – around 2000 pins in a single socket design. However if Skylake-EP is making the jump to a significantly larger socket, especially for 2P workstation and server designs, it will produce a spread of difference in potential for pricing structures and implementation.
The fourth possibility extends from the third, and that Skylake-EP will have two socket designs depending on the size of the core. For Broadwell-EP, there were three designs for the silicon underneath – a low core count (LCC), a medium core count (MCC) and an extreme core count (XCC). If Intel are splitting up the sockets, it may be the case that only the XCC or MCC+XCC sides of the equation are using LGA3647. LCC designs are typically used for the consumer E series parts anyway, so Intel may decide to make the low core designs of EP on the smaller socket. There’s a wealth of possibility here.
On the main Microsoft Azure page, a handy diagram of an example machine was provided (with some areas blacked out):
Here we see that motherboard from the image above, using two low profile heatsinks with copper piping feeding an optional heatsink inside the chassis. To the sides of each of the sockets are big black squares, indicating where the DDR4 memory should go. Nearer the bottom of the board are networking implementations (50G is labeled), and PCIe slots suitable for three full-height, half-length (FHHL) PCIe cards. Interestingly on the right-hand side, we have labeled ‘up to 8 M.2 NVMe SSDs’.
Back to the motherboard specification, we see the list of blacked out areas along with a more comprehensive sequence of potential configurations:
There are spots for up to 32 DIMMs, which makes 16 per socket. Depending on how many memory controllers the CPU has, this could mean 8-channel and 2 DIMMs per channel (DPC), or 4-channel and 4 DPC. Nowhere does it state the maximum DRAM support per CPU, but DDR4 LRDIMMs are currently at 256GB/module, meaning a potential maximum of 4TB per CPU or 8TB per system. We expect Skylake-EP to support 3D XPoint at some stage as well.
On that list of support also mentions up to 12 SATA devices, up to 3 FHHL cards, and two PCIe x8 slots capable of supporting two M.2 modules each. So this is where that 8x M.2 comes in – if we get four from two PCIe x8 slots, and combine this with up to four M.2 direct attach modules, that makes eight.
The top-level block diagram is also worth a look. Patrick from STH specifically points out the PCIe 3.0 support for the platform:
On the right-hand side, adding up all the PCIe numbers and it comes to 88 PCIe 3.0 lanes, or 44 per CPU. This would be an upgrade on the 40 lanes per CPU currently on Broadwell-EP. There is also provision for PCIe lanes to be used with the mini-SAS connectors on the left-hand side. Technically the BMC also requires a PCIe link as well.
Given the long product cycles of Intel’s EP platforms, and the fact that the Big Seven cloud providers have a lot of clout over sales means they are most likely testing and integrating the next generation hardware. The release to the public, and smaller players in the OCP space, is a long and slow one. We’re not expecting Skylake-E/EP out until well into 2017, if not the year after, so information will certainly be on the slow burn. Supercomputing 2016 is happening in Utah in a couple of weeks, and although we won’t be there due to scheduling, something may pop out of the woodwork. We’ll keep our eyes peeled.
Source: Microsoft, ServeTheHome
SuperComputing 15: Intel’s Knights Landing / Xeon Phi Silicon on Display
A Few Notes on Intel’s Knights Landing and MCDRAM Modes from SC15
The Next Generation Open Compute Hardware: Tried and Tested
The Intel Xeon E5 v4 Review: Testing Broadwell-EP With Demanding Server Workloads
Intel has already started to sell low-power dual-core Core i5/i7 Kaby Lake microprocessors for notebooks, but desktop parts with four cores and high frequencies are due in early 2017, as Intel announced back at IDF and the Kaby Lake-Y/U launch. In advance of the desktop launch, as is typical with how CPUs are launched, Intel has to send out qualification and near-retail samples to partners for pre-testing of release systems. Typically this is kept under wraps, without official public announcements (it’s up to you how many of the leaks you want to believe), but late last week Intel sent out a ‘Product Change Notification‘ through its online/public channels, with details about a good portion (no way to tell if it is all the SKUs) of Intel’s Core i7 and Core i5-7000 series parts.
Within the PCN, Intel notified its customers about an additional assembly/packaging site for its desktop Kaby Lake-S chips in Vietnam and therefore had to disclose model numbers of the CPUs as well as some of the specifications. In addition, in a separate PCN detailing package adjustments for how chipset ICs are shipped, it would seem that Intel has also mentioned names of its upcoming 200-series chipsets.
According to Intel’s document for partners, the company intends to release at least 11 quad-core processors for desktops based on the Kaby Lake microarchitecture in Q1. What is noteworthy is that the company wants its customers to get ready to receive the first shipments of the KBL-S chips assembled in Vietnam starting from November 4, 2016, this week (which means that the final specs of the new processors have been set and will only be changed in extreme circumstances). The initial KBL-S lineup would seem to include three Core i7 SKUs, seven Core i5 CPUs as well as one Xeon E3 v6 product. (The fact that a Xeon v6 is included in this is interesting, given that Intel removed standard chipset support for Xeon E3 CPUs with Skylake and v5, meaning that both consumer and enterprise platforms are due to land in January.)
All the Kaby Lake-S processors will use the B0 stepping of the core, and will have 100-300 MHz higher base frequency compared to their Skylake-S counterparts. The PCN does not explicitly state the TDP, however we do not expect much to change given the slightly improved 14+ nm technology and the increased frequencies (same thing applies to cache size, which has been consistent for several generations). We have already observed that mobile Kaby Lake CPUs have higher clock rates compared to their predecessors due to enhancements of Intel’s 14+ nm process technology, and we see that their desktop brethren also have improvements on this front. We do not have the final Turbo frequencies at hand, but we expect them to be considerably higher than the base clock rates.
| Basic Specifications of Quad-Core Intel Core i5/i5 and Xeon E3 | |||||||||
| Kaby Lake-S | Skylake-S | ||||||||
| Model | Cores /Threads |
Freq. (Base) |
TDP | Product Code |
S-Spec | Model | Freq. (Base) |
||
| i7-7700K | 4/8 | 4.2 GHz | 95W | CM8067702868535 | SR33A | i7-6700K | 4.0GHz | ||
| i7-7700 | 3.6 GHz | 65W | CM8067702868314 | SR338 | i7-6700 | 3.4GHz | |||
| i7-7700T | 2.9 GHz | 35W | CM8067702868416 | SR339 | i7-6700T | 2.8GHz | |||
| i5-7600K | 4/4 | 3.8 GHz | 95W | CM8067702868219 | SR32V | i5-6600K | 3.5GHz | ||
| i5-7600 | 3.5 GHz | 65W | CM8067702868011 | SR334 | i5-6600 | 3.3GHz | |||
| i5-7600T | 2.8 GHz | 35W | CM8067702868117 | SR336 | i5-6600T | 2.7GHz | |||
| i5-7500 | 3.4 GHz | 65W | CM8067702868012 | SR335 | i5-6500 | 3.2GHz | |||
| i5-7500T | 2.7 GHz | 35W | CM8067702868115 | SR337 | i5-6500T | 2.5GHz | |||
| i5-7400 | 3.0 GHz | 65W | CM8067702867050 | SR32W | i5-6400 | 2.7GHz | |||
| i5-7400T | 2.4 GHz | 35W | CM8067702867915 | SR332 | i5-6400T | 2.2GHz | |||
| E3-1205v6 | ?/? | 3.0 GHz | ? | CM8067702871025 | SR32D | – | – | ||
| Additional Info from Other Sources | |||||||||
| i3-7300* | 2/4 | 4.0 GHz | 65W | ? | SR2MC | i3-6300 | 3.8 GHz | ||
| Pentium G4620* | 2/2 | 3.8 GHz | 51W | ? | SR2HN | Pentium G4520 | 3.6 GHz | ||
| Pentium G3950* | 2/2 | 3.0 GHz | 51W | ? | SR2MU | Pentium G3920 | 2.9 GHz | ||
*CPU details taken from this piece at PCOnline
Aside from the 14+ process offering higher frequencies, the base microarchitecture of Kaby Lake-S, as explained at the release of Kaby Lake-Y/U in September, is essentially the same as Skylake. However, on top of increasing the frequencies, Intel is also adding in Speed Shift v2 which allows for much quicker adjustments in CPU frequency over Skylake (down to 10ms rather than 30ms).
It remains to be seen is whether the new 14+ process technology will also enable considerably higher overclocking potential compared to existing CPUs. If it does, then the new chips have a chance to become rather popular among enthusiasts, potentially toppling the i7-2600K as a long term favorite.
It might be noted is that Intel’s Kaby Lake-S will have to compete not only against their predecessors, but also against AMD’s Zen products due in Q1. That being said, some would argue that given AMD’s recent presentation of certain benchmark metrics, Zen is geared more towards the high-end desktop crowd. Nevertheless, it looks like early 2017 is going to be an interesting time for microprocessors.
In addition to model numbers of its Kaby Lake CPUs, Intel also revealed the names of its 200-series chipsets in another document it sent to partners. As expected, the lineup will include the Z270 PCH for enthusiast-class PCs with overclocking capabilities; Q270, H270 and H250 for mainstream systems and B250 for office/business computers.
| Intel 200-Series Chipsets | ||||||
| Name | Socket | Stepping | Product Code | S-Spec | ||
| Intel H270 | LGA1151 | A0 | GL82H270 | SR2WA | ||
| Intel Z270 | GL82Z270 | SR2WB | ||||
| Intel B250 | GL82B250 | SR2WC | ||||
| Intel Q250 | GL82Q250 | SR2WD | ||||
| Intel Q270 | GL82Q270 | SR2WE | ||||
| Intel C422 | LGA1151? | A0 | GL82C422 | SR2WG | ||
| Intel X299 | ?!? | A0 | GL82X299 | SR2Z2 | ||
Also in the list of chipsets were a couple of unknowns as well.
Listed in the PCN is C422, which because it has a ‘C’ in the name means that this is typically geared towards workstations and Xeon platforms. This may be in line with the E3-1205 v6 CPU SKU as seen in the processor list.
Also is X299, which really throws up a few question marks. The X-series chipsets are typically for Intel’s High-End Desktop Platform (HEDT), and we’ve had X58, X79 and X99 in the last decade, from Nehalem up to Broadwell-E which was released back in May. This means either one of two things – either Intel is bringing the X nomenclature to Kaby Lake, the mainstream platform, or this is the next chipset for HEDT and the future Skylake-E series of processors. The first option in making X299 a Kaby Lake-related platform seems a little odd. However the second one, with Skylake-E, makes sense. After X99, the X119 name doesn’t have the same marketability (if Intel was to keep parity with number jumps), but by pushing Skylake-E onto the 200-series naming as X299, it moves both mainstream and HEDT chipset naming strategies onto the same track. Note that we don’t have a time-frame for Skylake-E as of yet.
Intel’s motherboard customers, given the Q1 launch, must be ready to receive the 200-series PCH ICs on new reels. According to the PCN, these will come with additional protections bands starting from December 2, 2016. Intel may or may not announce the whole 200-series (not X) lineup at CES, given this late in the day adjustment to core components for the motherboards.
As for improvements of the Intel 200-series chipsets, we are still waiting on official confirmation as to exactly what to expect. Various unconfirmed leaks have indicated additional PCIe 3.0 chipset lanes, some new platform features and support for Intel’s Optane SSDs, however we will be here for the official launch when the time comes. It might be worth noting that almost all the motherboard manufacturers have now formally announced new 100-series BIOS support for Kaby Lake CPUs, meaning not all enthusiasts will have to get new motherboards.
Intel has already started to sell low-power dual-core Core i5/i7 Kaby Lake microprocessors for notebooks, but desktop parts with four cores and high frequencies are due in early 2017, as Intel announced back at IDF and the Kaby Lake-Y/U launch. In advance of the desktop launch, as is typical with how CPUs are launched, Intel has to send out qualification and near-retail samples to partners for pre-testing of release systems. Typically this is kept under wraps, without official public announcements (it’s up to you how many of the leaks you want to believe), but late last week Intel sent out a ‘Product Change Notification‘ through its online/public channels, with details about a good portion (no way to tell if it is all the SKUs) of Intel’s Core i7 and Core i5-7000 series parts.
Within the PCN, Intel notified its customers about an additional assembly/packaging site for its desktop Kaby Lake-S chips in Vietnam and therefore had to disclose model numbers of the CPUs as well as some of the specifications. In addition, in a separate PCN detailing package adjustments for how chipset ICs are shipped, it would seem that Intel has also mentioned names of its upcoming 200-series chipsets.
According to Intel’s document for partners, the company intends to release at least 11 quad-core processors for desktops based on the Kaby Lake microarchitecture in Q1. What is noteworthy is that the company wants its customers to get ready to receive the first shipments of the KBL-S chips assembled in Vietnam starting from November 4, 2016, this week (which means that the final specs of the new processors have been set and will only be changed in extreme circumstances). The initial KBL-S lineup would seem to include three Core i7 SKUs, seven Core i5 CPUs as well as one Xeon E3 v6 product. (The fact that a Xeon v6 is included in this is interesting, given that Intel removed standard chipset support for Xeon E3 CPUs with Skylake and v5, meaning that both consumer and enterprise platforms are due to land in January.)
All the Kaby Lake-S processors will use the B0 stepping of the core, and will have 100-300 MHz higher base frequency compared to their Skylake-S counterparts. The PCN does not explicitly state the TDP, however we do not expect much to change given the slightly improved 14+ nm technology and the increased frequencies (same thing applies to cache size, which has been consistent for several generations). We have already observed that mobile Kaby Lake CPUs have higher clock rates compared to their predecessors due to enhancements of Intel’s 14+ nm process technology, and we see that their desktop brethren also have improvements on this front. We do not have the final Turbo frequencies at hand, but we expect them to be considerably higher than the base clock rates.
| Basic Specifications of Quad-Core Intel Core i5/i5 and Xeon E3 | |||||||||
| Kaby Lake-S | Skylake-S | ||||||||
| Model | Cores /Threads |
Freq. (Base) |
TDP | Product Code |
S-Spec | Model | Freq. (Base) |
||
| i7-7700K | 4/8 | 4.2 GHz | 95W | CM8067702868535 | SR33A | i7-6700K | 4.0GHz | ||
| i7-7700 | 3.6 GHz | 65W | CM8067702868314 | SR338 | i7-6700 | 3.4GHz | |||
| i7-7700T | 2.9 GHz | 35W | CM8067702868416 | SR339 | i7-6700T | 2.8GHz | |||
| i5-7600K | 4/4 | 3.8 GHz | 95W | CM8067702868219 | SR32V | i5-6600K | 3.5GHz | ||
| i5-7600 | 3.5 GHz | 65W | CM8067702868011 | SR334 | i5-6600 | 3.3GHz | |||
| i5-7600T | 2.8 GHz | 35W | CM8067702868117 | SR336 | i5-6600T | 2.7GHz | |||
| i5-7500 | 3.4 GHz | 65W | CM8067702868012 | SR335 | i5-6500 | 3.2GHz | |||
| i5-7500T | 2.7 GHz | 35W | CM8067702868115 | SR337 | i5-6500T | 2.5GHz | |||
| i5-7400 | 3.0 GHz | 65W | CM8067702867050 | SR32W | i5-6400 | 2.7GHz | |||
| i5-7400T | 2.4 GHz | 35W | CM8067702867915 | SR332 | i5-6400T | 2.2GHz | |||
| E3-1205v6 | ?/? | 3.0 GHz | ? | CM8067702871025 | SR32D | – | – | ||
| Additional Info from Other Sources | |||||||||
| i3-7300* | 2/4 | 4.0 GHz | 65W | ? | SR2MC | i3-6300 | 3.8 GHz | ||
| Pentium G4620* | 2/2 | 3.8 GHz | 51W | ? | SR2HN | Pentium G4520 | 3.6 GHz | ||
| Pentium G3950* | 2/2 | 3.0 GHz | 51W | ? | SR2MU | Pentium G3920 | 2.9 GHz | ||
*CPU details taken from this piece at PCOnline
Aside from the 14+ process offering higher frequencies, the base microarchitecture of Kaby Lake-S, as explained at the release of Kaby Lake-Y/U in September, is essentially the same as Skylake. However, on top of increasing the frequencies, Intel is also adding in Speed Shift v2 which allows for much quicker adjustments in CPU frequency over Skylake (down to 10ms rather than 30ms).
It remains to be seen is whether the new 14+ process technology will also enable considerably higher overclocking potential compared to existing CPUs. If it does, then the new chips have a chance to become rather popular among enthusiasts, potentially toppling the i7-2600K as a long term favorite.
It might be noted is that Intel’s Kaby Lake-S will have to compete not only against their predecessors, but also against AMD’s Zen products due in Q1. That being said, some would argue that given AMD’s recent presentation of certain benchmark metrics, Zen is geared more towards the high-end desktop crowd. Nevertheless, it looks like early 2017 is going to be an interesting time for microprocessors.
In addition to model numbers of its Kaby Lake CPUs, Intel also revealed the names of its 200-series chipsets in another document it sent to partners. As expected, the lineup will include the Z270 PCH for enthusiast-class PCs with overclocking capabilities; Q270, H270 and H250 for mainstream systems and B250 for office/business computers.
| Intel 200-Series Chipsets | ||||||
| Name | Socket | Stepping | Product Code | S-Spec | ||
| Intel H270 | LGA1151 | A0 | GL82H270 | SR2WA | ||
| Intel Z270 | GL82Z270 | SR2WB | ||||
| Intel B250 | GL82B250 | SR2WC | ||||
| Intel Q250 | GL82Q250 | SR2WD | ||||
| Intel Q270 | GL82Q270 | SR2WE | ||||
| Intel C422 | LGA1151? | A0 | GL82C422 | SR2WG | ||
| Intel X299 | ?!? | A0 | GL82X299 | SR2Z2 | ||
Also in the list of chipsets were a couple of unknowns as well.
Listed in the PCN is C422, which because it has a ‘C’ in the name means that this is typically geared towards workstations and Xeon platforms. This may be in line with the E3-1205 v6 CPU SKU as seen in the processor list.
Also is X299, which really throws up a few question marks. The X-series chipsets are typically for Intel’s High-End Desktop Platform (HEDT), and we’ve had X58, X79 and X99 in the last decade, from Nehalem up to Broadwell-E which was released back in May. This means either one of two things – either Intel is bringing the X nomenclature to Kaby Lake, the mainstream platform, or this is the next chipset for HEDT and the future Skylake-E series of processors. The first option in making X299 a Kaby Lake-related platform seems a little odd. However the second one, with Skylake-E, makes sense. After X99, the X119 name doesn’t have the same marketability (if Intel was to keep parity with number jumps), but by pushing Skylake-E onto the 200-series naming as X299, it moves both mainstream and HEDT chipset naming strategies onto the same track. Note that we don’t have a time-frame for Skylake-E as of yet.
Intel’s motherboard customers, given the Q1 launch, must be ready to receive the 200-series PCH ICs on new reels. According to the PCN, these will come with additional protections bands starting from December 2, 2016. Intel may or may not announce the whole 200-series (not X) lineup at CES, given this late in the day adjustment to core components for the motherboards.
As for improvements of the Intel 200-series chipsets, we are still waiting on official confirmation as to exactly what to expect. Various unconfirmed leaks have indicated additional PCIe 3.0 chipset lanes, some new platform features and support for Intel’s Optane SSDs, however we will be here for the official launch when the time comes. It might be worth noting that almost all the motherboard manufacturers have now formally announced new 100-series BIOS support for Kaby Lake CPUs, meaning not all enthusiasts will have to get new motherboards.
