Today ARM is announcing an update to their line of architecture license products. With the goal of moving ARM more into the server, the data center, and high-performance computing, the new license add-on tackles a fundamental data center and HPC issue…
As part of today’s announcements, we’re able to provide more information on ARM’s new “Built on ARM Cortex Technology” license. The license was first officially revealed in ARM’s quartely financial call back in February, however at the time the company wasn’t ready to talk about the exact details of this new license.
We covered ARM’s business and licensing models back a few years ago in a dedicated article which goes into more depth what kind of options vendors have when deciding to license an ARM IP. ARM likes to represent the licensing model in a pyramid shape with increasing cost and involvement the higher you get on the pyramid. Until now vendors had two main choices: Use one of the various available Cortex licenses, or get an architectural license and develop one’s own microarchitecture based on ARM’s ISA.
The former licensing options varied depending on what kind of engagement and deployment a vendor is looking for. Lead licensees for example get early access to new microarchitectures but also have to pay more for this access and it’s possible that they will have to deal with still immature toolkits and documentation, both which would then require more invovement and investment on their part. Vendors who are willing to wait a bit more or who aren’t looking in an as deep engagement are able to use some of the cheaper licenses and more mature tools and documentation.
The common limitation of all current Cortex licenses however is that a vendor is not able to change any aspect of the microarchitecture. If a customer needed a feature that ARM’s cores didn’t provide, they had to go with an architectural license and develop their own microarchitecture from scratch. Currently examples of such licensees with shipping custom microarchitectures include Apple, Qualcomm and Samsung.
The new license being detailed today is the “Built on ARM Cortex Technology” license, which is quite a mouthfull and will unofficially refer to as “Built on Cortex”/BoC from here on. The new BoC license represents a new “tip of the pyramid” for Cortex licenses with even greater engagement than that of lead licensees.
The new license allows vendors to request changes of an ARM microarchitecture and use this customized IP in their products. The way this works is that basically ARM provides its engineering and design services to the vendor who wants a certain aspect of an “off-the-shelf” Cortex design customized. Under the license’s terms, ARM still owns and controls the IP, however the changes requested for that particular vendor’s design is not shared or made available to other vendors.
An example of a customization that a vendor would be able to request is the instruction window size. An increase in the instruction window size would increase the IPC of a microarchitecture, however this can cause higher area and power which would need to be compensated by more implementation work by the vendor.
While ARM didn’t want to go into details of what other customization options a vendor would have, they say that it will have a rather limited scope and things such as altering decoder width or changing the execution resources of a microarchitecture are beyond the scope of the license. In general, it seems more that the license is meant to allow vendors to tweak and configure the knobs on some aspects of a microarchitecture rather than do significant changes to the way the µarch works.
What is in my view the most important and controversial aspect of the new license is that it allows vendors full branding freedom on this customized CPU design. This means that a Built on Cortex licensee is free to give the resulting new core any name it sees fit. We’ll however still be able to differentiate the core from a full custom microarchitecture as ARM still requires a disclaimer / footnote / subtitle with the “Built on ARM Cortex Technology” phrase.
In February ARM disclosed that Qualcomm is the first costumer signed up for this license, and what this means for the Snapdragon SoC lineup is currently still unclear. If this new licensing model will be able to allow vendors to truly differentiate their products beyond just the marketing aspect is something we won’t know until the first designs come out and will be tested, and until then, the verdict on ARM’s new license is still open.
As part of today’s announcements, we’re able to provide more information on ARM’s new “Built on ARM Cortex Technology” license. The license was first officially revealed in ARM’s quartely financial call back in February, however at the time the company wasn’t ready to talk about the exact details of this new license.
We covered ARM’s business and licensing models back a few years ago in a dedicated article which goes into more depth what kind of options vendors have when deciding to license an ARM IP. ARM likes to represent the licensing model in a pyramid shape with increasing cost and involvement the higher you get on the pyramid. Until now vendors had two main choices: Use one of the various available Cortex licenses, or get an architectural license and develop one’s own microarchitecture based on ARM’s ISA.
The former licensing options varied depending on what kind of engagement and deployment a vendor is looking for. Lead licensees for example get early access to new microarchitectures but also have to pay more for this access and it’s possible that they will have to deal with still immature toolkits and documentation, both which would then require more invovement and investment on their part. Vendors who are willing to wait a bit more or who aren’t looking in an as deep engagement are able to use some of the cheaper licenses and more mature tools and documentation.
The common limitation of all current Cortex licenses however is that a vendor is not able to change any aspect of the microarchitecture. If a customer needed a feature that ARM’s cores didn’t provide, they had to go with an architectural license and develop their own microarchitecture from scratch. Currently examples of such licensees with shipping custom microarchitectures include Apple, Qualcomm and Samsung.
The new license being detailed today is the “Built on ARM Cortex Technology” license, which is quite a mouthfull and will unofficially refer to as “Built on Cortex”/BoC from here on. The new BoC license represents a new “tip of the pyramid” for Cortex licenses with even greater engagement than that of lead licensees.
The new license allows vendors to request changes of an ARM microarchitecture and use this customized IP in their products. The way this works is that basically ARM provides its engineering and design services to the vendor who wants a certain aspect of an “off-the-shelf” Cortex design customized. Under the license’s terms, ARM still owns and controls the IP, however the changes requested for that particular vendor’s design is not shared or made available to other vendors.
An example of a customization that a vendor would be able to request is the instruction window size. An increase in the instruction window size would increase the IPC of a microarchitecture, however this can cause higher area and power which would need to be compensated by more implementation work by the vendor.
While ARM didn’t want to go into details of what other customization options a vendor would have, they say that it will have a rather limited scope and things such as altering decoder width or changing the execution resources of a microarchitecture are beyond the scope of the license. In general, it seems more that the license is meant to allow vendors to tweak and configure the knobs on some aspects of a microarchitecture rather than do significant changes to the way the µarch works.
What is in my view the most important and controversial aspect of the new license is that it allows vendors full branding freedom on this customized CPU design. This means that a Built on Cortex licensee is free to give the resulting new core any name it sees fit. We’ll however still be able to differentiate the core from a full custom microarchitecture as ARM still requires a disclaimer / footnote / subtitle with the “Built on ARM Cortex Technology” phrase.
In February ARM disclosed that Qualcomm is the first costumer signed up for this license, and what this means for the Snapdragon SoC lineup is currently still unclear. If this new licensing model will be able to allow vendors to truly differentiate their products beyond just the marketing aspect is something we won’t know until the first designs come out and will be tested, and until then, the verdict on ARM’s new license is still open.
We covered the news of the first shipment of 64-bit ARMv8 processors in the HP Moonshot product line earlier this week. At ARM TechCon 2014, Applied Micro (APM) had a very interesting update to their 64-bit ARM v8 product line. They launched two SoC families, HeliX 1 and HeliX 2. Both of them are based on the X-Gene ARMv8 cores developed for servers, but appropriately scaled down to fit in the 8 W – 42 W TDP scenarios for the embedded market. The HeliX 1 is fabricated in a 40 nm process, while the HeliX 2 uses a 28 nm process. The latter uses the second generation X-Gene ARMv8 core.
Applied Micro has traditionally been a PowerPC house. In fact, we have evaluated their Catalina networked storage platform in the Thecus N2310 and looked at the previous generation PowerPC SoC in the Western Digital My Book Live. However, in 2010, Applied Micro obtained an architecture license for ARMv8 (the 64-bit ARM architecture). Understanding that PowerPC was in decline, Applied Micro decided to devote all development resources to ARMv8. As part of this deal, all product lines based on the PowerPC architecture are being migrated to ARMv8 under the HeliX family.
APM is hoping to get HeliX into the embedded market, with focus on communication and networking, imaging, storage and industrial computing verticals. They believe ARMv8 is the architecture of the future and had a number of companies (including Cisco, Netgear, Konica Minolta, Wind River and Canonical) voicing support for their strategy.
The two SoC product lines launched by APM yesterday were the APM887208-H1 (based on HeliX 1) and the APM887104-H2 (based on HeliX 2). The SoC block diagrams of both of these SoCs are provided below, along with a table summarizing and comparing the various aspects.
Applied Micro Helix Block Diagram
| Applied Micro HeliX Family | ||||
| APM887208-H1 | APM887104-H2 | |||
| Cores | 4 or 8 ARMv8 HeliX 1 at up to 2.4 GHz | 2 or 4 ARMv8 HeliX 2 at up to 2.0 GHz | ||
| L1 Cache | 32 KB I / 32 KB D per core (write-through with parity protection) | |||
| L2 Cache | 256 KB shared per core pair (with ECC) 64 | |||
| L3 Cache | 4 or 8 MB shared | 2 MB shared | ||
| DRAM | 2x DDR3 Controllers with ECC (72b each) | 1x DDR3 Controller with ECC (72b) | ||
| On-Chip Memory | 1 MB | 256 KB | ||
| Memory Bus Width | 256-bit | 256-bit | ||
| Low Power Features | N/A | < 250 mW standby | ||
| Coprocessors | 4x Cortex-A5 at 500 MHz | N/A | ||
| High-Speed Interfaces | 2x 10G + 4x 1G + 1x 1G Management Ethernet | 1x 10G + 4x 1G Ethernet | ||
| 17x PCIe 3.0 (2 x8 + 1 x1 OR 1 x8 + 2 x4 + 1 x1 OR 4 x4 + 1 x1) | 3x PCIe 3.0 (2 x1 OR 1 x4) | |||
|
|
2x USB 3.0 Host + 1x USB 3.0 Host/Device | |||
| 6x SATA III (four muxed with 4x 1G Ethernet) | 1x SATA III | |||
Applied Micro Helix 2 Block Diagram
The HeliX SoCs are sampling right now and slated to go into volume production in 2015. Applied Micro claims that design wins are already in place. From ARM’s perspective, one can say that the juggernaut rolls on. With Cavium’s Project Thunder and Broadcom’s Vulcan targeting the high-end enterprise and datacenter segment, ARM needed an entry in the mid- to high-end embedded space currently dominated by MIPS64 and x86-64. The Applied Micro HeliX family brings ARM forward as a credible competitor for those sockets.
We covered the news of the first shipment of 64-bit ARMv8 processors in the HP Moonshot product line earlier this week. At ARM TechCon 2014, Applied Micro (APM) had a very interesting update to their 64-bit ARM v8 product line. They launched two SoC families, HeliX 1 and HeliX 2. Both of them are based on the X-Gene ARMv8 cores developed for servers, but appropriately scaled down to fit in the 8 W – 42 W TDP scenarios for the embedded market. The HeliX 1 is fabricated in a 40 nm process, while the HeliX 2 uses a 28 nm process. The latter uses the second generation X-Gene ARMv8 core.
Applied Micro has traditionally been a PowerPC house. In fact, we have evaluated their Catalina networked storage platform in the Thecus N2310 and looked at the previous generation PowerPC SoC in the Western Digital My Book Live. However, in 2010, Applied Micro obtained an architecture license for ARMv8 (the 64-bit ARM architecture). Understanding that PowerPC was in decline, Applied Micro decided to devote all development resources to ARMv8. As part of this deal, all product lines based on the PowerPC architecture are being migrated to ARMv8 under the HeliX family.
APM is hoping to get HeliX into the embedded market, with focus on communication and networking, imaging, storage and industrial computing verticals. They believe ARMv8 is the architecture of the future and had a number of companies (including Cisco, Netgear, Konica Minolta, Wind River and Canonical) voicing support for their strategy.
The two SoC product lines launched by APM yesterday were the APM887208-H1 (based on HeliX 1) and the APM887104-H2 (based on HeliX 2). The SoC block diagrams of both of these SoCs are provided below, along with a table summarizing and comparing the various aspects.
Applied Micro Helix Block Diagram
| Applied Micro HeliX Family | ||||
| APM887208-H1 | APM887104-H2 | |||
| Cores | 4 or 8 ARMv8 HeliX 1 at up to 2.4 GHz | 2 or 4 ARMv8 HeliX 2 at up to 2.0 GHz | ||
| L1 Cache | 32 KB I / 32 KB D per core (write-through with parity protection) | |||
| L2 Cache | 256 KB shared per core pair (with ECC) 64 | |||
| L3 Cache | 4 or 8 MB shared | 2 MB shared | ||
| DRAM | 2x DDR3 Controllers with ECC (72b each) | 1x DDR3 Controller with ECC (72b) | ||
| On-Chip Memory | 1 MB | 256 KB | ||
| Memory Bus Width | 256-bit | 256-bit | ||
| Low Power Features | N/A | < 250 mW standby | ||
| Coprocessors | 4x Cortex-A5 at 500 MHz | N/A | ||
| High-Speed Interfaces | 2x 10G + 4x 1G + 1x 1G Management Ethernet | 1x 10G + 4x 1G Ethernet | ||
| 17x PCIe 3.0 (2 x8 + 1 x1 OR 1 x8 + 2 x4 + 1 x1 OR 4 x4 + 1 x1) | 3x PCIe 3.0 (2 x1 OR 1 x4) | |||
|
|
2x USB 3.0 Host + 1x USB 3.0 Host/Device | |||
| 6x SATA III (four muxed with 4x 1G Ethernet) | 1x SATA III | |||
Applied Micro Helix 2 Block Diagram
The HeliX SoCs are sampling right now and slated to go into volume production in 2015. Applied Micro claims that design wins are already in place. From ARM’s perspective, one can say that the juggernaut rolls on. With Cavium’s Project Thunder and Broadcom’s Vulcan targeting the high-end enterprise and datacenter segment, ARM needed an entry in the mid- to high-end embedded space currently dominated by MIPS64 and x86-64. The Applied Micro HeliX family brings ARM forward as a credible competitor for those sockets.